Mạch Logic 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lg is
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(5 downto 0)
);
end lg;

architecture lg of lg is
begin
z(5) <= a and b;
z(4) <= a nand b;
z(3) <= a or b;
z(2) <= a nor b;
z(1) <= a xor b;
z(0) <= a xnor b;
end lg;