library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity hex7segc is
port (
x: in STD_LOGIC_VECTOR(2 downto 0);
y : out STD_LOGIC_VECTOR(6 downto 0)
);
end hex7segc;
architecture hex7seg of hex7segc is
begin
process(x)
begin
case x is
when "000" => y <= "0000001"; --0
when "001" => y <= "1001111"; --1
when "010" => y <= "0010010"; --2
when "011" => y <= "0000110"; --3
when "100" => y <= "1001100"; --4
when "101" => y <= "0100100"; --5
when "110" => y <= "0100000"; --6
when "111" => y <= "0001111"; --7
when others => null;
end case;
end process;
end hex7seg;
Tương tự như bài này :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity hex7segb is
port (
x: in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0)
);
end hex7segb;
architecture hex7seg of hex7segb is
begin
process(x)
begin
case x is
when "0000" => a_to_g <= "0000001"; --0
when "0001" => a_to_g <= "1001111"; --1
when "0010" => a_to_g <= "0010010"; --2
when "0011" => a_to_g <= "0000110"; --3
when "0100" => a_to_g <= "1001100"; --4
when "0101" => a_to_g <= "0100100"; --5
when "0110" => a_to_g <= "0100000"; --6
when "0111" => a_to_g <= "0001111"; --7
when "1000" => a_to_g <= "0000000"; --8
when "1001" => a_to_g <= "0000100"; --9
when "1010" => a_to_g <= "0001000"; --A
when "1011" => a_to_g <= "1100000"; --b
when "1100" => a_to_g <= "0110001"; --C
when "1101" => a_to_g <= "1000010"; --d
when "1110" => a_to_g <= "0110000"; --E
when others => a_to_g <= "0111000"; --F
end case;
end process;
end hex7seg;
đếm từ 7 về 0
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