Thiết kế RS-FF

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity RSFF is
port(
R : in STD_LOGIC;
S : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC
);
end RSFF;

architecture RSFF of RSFF is
signal q0: std_logic;
begin
process (CLK,RST,R,S)
variable RS:std_logic_vector (1 downto 0);
begin
RS:=R&S;
if (RST='1') then
q0<='0';
else if (CLK'event and CLK='1') then
case RS is
when "00"=>q0<=q0;
when "01"=>q0<='1';
when "10"=>q0<='0';
when others=>q0<='X';
end case;
end if;
end if;
end process;
Q<=q0;
end RSFF;